The present invention relates generally to an information (data) processing system, and particularly to a virtual machine system suited advantageously for allowing a plurality of operating systems to run on an information processing system.
In field of the information or data processing techniques, there has already been proposed a virtual machine system of multi-processor configuration (or multi-processor virtual machine system) in which a plurality of real instruction processors (IPs) are assigned to and operate for several virtual machines. A technique for supporting such a virtual machine system is described, for example, in "IBM System/370 Extended Architecture Interpretive Execution SA22-7095", January, 1984.
Heretofore, in order to allow a computer system of the multi-processor configuration to operate correctly as an information processing system, such an arrangement has generally been adopted in which when the content of a main storage is updated as the result of an instruction execution in an instruction processor, a signal for invalidation of an entry of each buffer storage which is incorporated in each instruction processor and each of which contains a copy of the content of the main storage, is sent to the individual instruction processors, whereupon the invalidation of the entry of the buffer storage is performed in each instruction processor. Also in the case of the virtual machine system of multi-processor configuration which is implemented so as to operate on the information processing system which has the above-mentioned arrangement with the main storage, the instruction processors and others being divided and allocated to the individual virtual machines, there may arise a possibility that unnecessary invalidation of the entries of the buffer storages incorporated in the virtual machines, respectively, will uselessly be performed even by the instruction processors assigned to the other virtual machines which are not directly relevant to the execution of the instruction, since the signal for invalidating the entry of the buffer storage is issued to all the instruction processors assigned to the virtual machines. Particularly in the case of the information processing system in which the address of the entry of the buffer storage is not defined by using all the bits of the corresponding address of the main storage but by using only a part of the bits, there may arise such situation in which the same entry address of buffer storage may be given for different addresses of the main storage, resulting in that invalidation in excess may be effectuated, whereby the processing efficiency of the whole system will ultimately be lowered to great disadvantage. Further, when an instruction for invalidating the entry of a TLB (address translation buffer) is executed, a signal for invalidating the entry of the TLB is also sent to all the instruction processors, which means that excessive invalidation of the entries of the TLBs may take place in the instruction processors assigned to the other virtual machines. Besides, when the entry address of TLB is defined by a part of the virtual storage address, invalidation in excess may also take place, whereby the processing efficiency of the whole system may unwantedly be degraded.